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FEATURES
Preliminary Technical Data
Dual Symmetric 600 Mhz High Performance Blackfin Core 328 KBytes of On-chip Memory (See Memory Info on Page 3) Each Blackfin Core Includes: Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs, 40-Bit Shifter RISC-Like Register and Instruction Model for Ease of Programming and Compiler-Friendly Support Advanced Debug, Trace, and Performance- Monitoring 0.8 - 1.2V core VDD with On-Chip Voltage Regulation 3.3V and 2.5V Tolerant I/O 256-Ball Mini BGA and 297-Ball PBGA Package Options
Blackfin(R) Embedded Symmetric Multi-Processor ADSP-BF561
PERIPHERALS
Two Parallel Input/Output Peripheral Interface Units Supporting ITU-R 656 Video and Glueless Interface to ADI Analog Front End ADCs Two Dual Channel, Full Duplex Synchronous Serial Ports Supporting Eight Stereo I2S Channels Dual 16 Channel DMA Controllers and one internal memory DMA controller 12 General Purpose 32-bit Timer/Counters, with PWM Capability SPI-Compatible Port UART with Support for IrDA(R) Dual Watchdog Timers 48 Programable Flags On-Chip Phase Locked Loop Capable of 1x to 63x Frequency Multiplication
IRQ CTRL/ TIMER VOLTAGE REGULATOR
B
L1 INSTRUCTION MEMORY MMU L1 DATA MEMORY
B
L1 INSTRUCTION MEMORY MMU L1 DATA MEMORY
IRQ CTRL/ TIMER
JTAG TEST EMULATION UART IRDA(R)
SPI
L2 SRAM 128 KBYTES
SPORT0
CORE SYSTEM / BUS INTERFACE
IMDMA CONTROLLER
SPORT1
EAB DMA CONTROLLER1 32 DMA CONTROLLER2 BOOT ROM 32 DAB DAB PAB 16 16
GPIO
TIMERS
EXTERNAL PORT FLASH/SDRAM CONTROL
PPI
PPI
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADSP-BF561
TABLE OF CONTENTS
General Description ................................................. 3 Portable Low-Power Architecture ............................. 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 4 Internal (On-chip) Memory ................................. 4 External (Off-Chip) Memory ................................ 5 I/O Memory Space ............................................. 6 Booting ........................................................... 6 Event Handling ................................................. 6 Core Event Controller (CEC) ................................ 6 System Interrupt Controller (SIC) .......................... 6 Event Control ................................................... 7 DMA Controllers .................................................. 8 WatchDog Timers ................................................ 8 Serial Ports (SPORTs) ............................................ 9 Serial Peripheral Interface (SPI) Ports ........................ 9 UART Port .......................................................... 9 Programmable Flags (PFx) .................................... 10 Timers ............................................................. 10 Parallel Peripheral Interface ................................... 10 General Purpose Mode Descriptions .................... 10 Input Mode .................................................... 10 ITU -R 656 Mode Descriptions ........................... 10 Active Video Only Mode ................................... 10 Vertical Blanking Interval Mode .......................... 11 Entire Field Mode ............................................ 11 Dynamic Power Management ................................ 11 Full-On Operating Mode - Maximum Performance . 11 Active Operating Mode - Moderate Power Savings .. 11 Hibernate Operating Mode--Maximum Static Power Savings ....................................................... 11 Sleep Operating Mode - High Power Savings ......... 11 Deep Sleep Operating Mode - Max. Power Savings .. 11 Power Savings ................................................. 12 Voltage Regulation .............................................. 12 Clock Signals ..................................................... 13 Booting Modes ................................................... 13 Instruction Set Description ................................... 14
Preliminary Technical Data
Development Tools .............................................. 14 Designing an Emulator-Compatible Processor Board (Target) ................................... 15 Additional Information ........................................ 15 Pin Descriptions .................................................... 16 Specifications ........................................................ 20 Recommended Operating Conditions ...................... 20 Electrical Characteristics ....................................... 20 Absolute Maximum Ratings ................................... 21 ESD Sensitivity ................................................... 21 Timing Specifications ........................................... 22 Clock and Reset Timing ..................................... 23 Asynchronous Memory Read Cycle Timing ............ 24 Asynchronous Memory Write Cycle Timing ........... 25 SDRAM Interface Timing .................................. 26 External Port Bus Request and Grant Cycle Timing .. 27 Parallel Peripheral Interface Timing ..................... 28 Serial Ports ..................................................... 29 Serial Peripheral Interface (SPI) Port--Master Timing 34 Serial Peripheral Interface (SPI) Port--Slave Timing . 36 Universal Asynchronous Receiver-Transmitter (UART) Port--Receive and Transmit Timing .................. 38 Timer Cycle Timing .......................................... 39 Programmable Flags Cycle Timing ....................... 40 JTAG Test And Emulation Port Timing ................. 41 Power Dissipation ............................................... 42 Output Drive Currents ......................................... 42 Test Conditions .................................................. 42 Output Enable Time ......................................... 43 Output Disable Time ......................................... 43 Example System Hold Time Calculation ................... 43 Capacitive Loading .............................................. 44 256-ball MBGA Pin Configurations ............................ 45 297-ball PBGA Pin Configurations ............................. 47 Outline Dimensions ................................................ 50 Outline Dimensions ................................................ 51 Ordering Guide ..................................................... 51
REVISION HISTORY
Revision PrC: * Edits made to pinlists and timing specification.
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Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-BF561 processor is a high-performance member of the Blackfin family of products targeting a variety of multimedia and telecommunications applications. At the heart of this device are two independent Analog Devices Blackfin processors. These Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantage of a clean, orthogonal RISClike microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The ADSP-BF561 device integrates a general purpose set of digital imaging peripherals creating a complete system on-chip solution for digital imaging and multimedia applications. The ADSP-BF561 processor has 328 KBytes of on-chip memory. Each Blackfin core includes: * 16K Bytes of Instruction SRAM/Cache * 16K Bytes of Instruction SRAM * 32K Bytes of Data SRAM/Cache * 32K Bytes of Data SRAM * 4K Bytes of Scratchpad SRAM
ADSP-BF561
Additional on-chip memory peripherals include: * 128 KBytes of Low Latency On-chip SRAM * Four Channel Internal Memory DMA Controller * External Memory controller with glueless support for SDRAM, SRAM, and Flash
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management and performance for embedded signal processing applications. Blackfin processors are designed in a low power and low voltage design methodology and feature Dynamic Power Management. Dynamic Power Management is the ability to vary both the voltage and frequency of operation to significantly lower the overall power dissipation. This translates into an exponential reduction in power dissipation providing longer battery life to portable applications.
BLACKFIN PROCESSOR CORE
As shown in Figure 2, each Blackfin core contains two multiplier/accumulators (MACs), two 40-bit ALUs, four video ALUs, and a single shifter. The computational units process 8-bit, 16bit, or 32-bit data from the register file.
ADDRESS ARITHMETIC UNIT
SP FP P5 P4 P3 P2 P1 P0
I3 I2 I1 I0
L3 L2 L1 L0
B3 B2 B1 B0
M3 M2 M1 M0
DAG0
DAG1
SEQUENCER
ALIGN
DECODE R7 R6 R5 R4 R3 R2 R1 R0 16 8 8 8 16 8 CONTROL UNIT
LOOP BUFFER
BARREL SHIFTER
40
40
A0
A1
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
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ADSP-BF561
Each MAC performs a 16-bit by 16-bit multiply in every cycle, with an accumulation to a 40-bit result, providing 8 bits of extended precision. The ALUs perform a standard set of arithmetic and logical operations. With two ALUs capable of operating on 16- or 32-bit data, the flexibility of the computation units covers the signal processing requirements of a varied set of application needs. Each of the two 32-bit input registers can be regarded as two 16bit halves, so each ALU can accomplish very flexible single 16bit arithmetic operations. By viewing the registers as pairs of 16bit operands, dual 16-bit or single 32-bit operations can be accomplished in a single cycle. By further taking advantage of the second ALU, quad 16-bit operations can be accomplished simply, accelerating the per cycle throughput. The powerful 40-bit shifter has extensive capabilities for performing shifting, rotating, normalization, extraction, and depositing of data. The data for the computational units is found in a multi-ported register file of sixteen 16-bit entries or eight 32-bit entries. A powerful program sequencer controls the flow of instruction execution, including instruction alignment and decoding. The sequencer supports conditional jumps and subroutine calls, as well as zero-overhead looping. A loop buffer stores instructions locally, eliminating instruction memory accesses for tight looped code. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from memory. The DAGs share a register file containing four sets of 32-bit Index, Modify, Length, and Base registers. Eight additional 32-bit registers provide pointers for general indexing of variables and stack locations. Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. Level 2 (L2) memories are other memories, on-chip or off-chip, that may take multiple processor cycles to access. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. At the L2 level, there is a single unified memory space, holding both instructions and data. In addition, half of L1 instruction memory and half of L1 data memories may be configured as either Static RAMs (SRAMs) or caches. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be operating on the core and may protect system registers from unintended access. The architecture provides three modes of operation: User mode, Supervisor mode, and Emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin instruction set has been optimized so that 16-bit op-codes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit op-codes, representing fully featured multifunction instructions. Blackfin processors supRev. PrC |
Preliminary Technical Data
port a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the VisualDSP C/C++ compiler, resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF561 views memory as a single unified 4G-byte address space, using 32-bit addresses. All resources including internal memory, external memory, and I/O control registers occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency memory as cache or SRAM very close to the processor, and larger, lower-cost and performancememory systems farther away from the processor. The ADSPBF561 memory map is shown in Figure 3. The L1 memory system in each core is the highest-performance memory available to each Blackfin core. The L2 memory provides additional capacity with lower performance. Lastly, the off-chip memory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing more than 768M bytes of physical memory. The memory DMA controllers provide high-bandwidth data-movement capability. They can perform block transfers of code or data between the internal L1/L2 memories and the external memory spaces.
Internal (On-chip) Memory
The ADSP-BF561 has four blocks of on-chip memory providing high-bandwidth access to the core. The first is the L1 instruction memory of each Blackfin core consisting of 16K bytes of 4-way set-associative cache memory and 16K bytes of SRAM. The cache memory may also be configured as an SRAM. This memory is accessed at full processor speed. When configured as SRAM, each of the two 16K banks of memory is broken into 4K sub-banks which can be independently accessed by the processor and DMA. The second on-chip memory block is the L1 data memory of each Blackfin core which consists of four banks of 16K bytes each. Two of the L1 data memory banks can be configured as one way of a two-way set associative cache or as an SRAM. The other two banks are configured as SRAM. All banks are accessed at full processor speed. When configured as SRAM, each of the four 16K banks of memory is broken into 4K sub-banks which can be independently accessed by the processor and DMA. The third memory block associated with each core is a 4K-byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM (it cannot be configured as cache memory and is not accessible via DMA).
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Preliminary Technical Data
COREAM O EM RYM AP 0xFFFFFFFF 0xFFE00000 0xFFC00000 0xFFB01000 0xFFB00000 0xFFA14000 0xFFA10000 0xFFA04000 0xFFA00000 0xFF908000 0xFF904000 0xFF900000 0xFF808000 0xFF804000 0xFF800000 RESERVE D L1SCRATCHPADSRAM(4K) RESERVE D L1INSTRUCTIONSRAM /CACHE(16K) RESERVE D L1INSTRUCTIONSRAM(16K) RESERVE D L1DATABANKBSRAM /CACHE(16K) L1DATABANKBSRAM(16K) RESERVE D L1DATABANKASRAM /CACHE(16K) L1DATABANKASRAM(16K) RESE RVED L1SCRATCHPADS RAM(4K) RESE RVED L1INSTRUCTIONSRAM /CACHE(16K) RESE RVED RESERVED L1INSTRUCTIONSRAM(16K) RESE RVED L1DATABANKBSRAM /CACHE(16K) L1DATABANKBSRAM(16K) RESE RVED L1DATABANKASRAM /CACHE(16K) L1DATABANKASRAM(16K) 0xFEB20000 0xFEB00000 0xEF004000 0xEF000000 0x30000000 0x2C000000 0x28000000 0x24000000 0x20000000 Topof last SDRAMpage RES ERVED L2SRAM(128K) RESERVED BO OTRO M RESERVED ASYNCM O EM RYBANK3 ASYNCM O EM RYBANK2 ASYNCM O EM RYBANK1 ASYNCM O EM RYBANK0 RESERVED S DRAMBANK3 S DRAMBANK2 S DRAMBANK1 0x00000000 S DRAMBANK0 EX TERNALM O EM RY 0xFF800000 0xFF701000 0xFF700000 0xFF614000 0xFF610000 0xFF604000 0xFF600000 0xFF508000 0xFF504000 0xFF500000 0xFF408000 0xFF404000 0xFF400000 INTERNALM O EM RY RESE RVED CO REM RREG M ISTERS CO REM RREGISTERS M SYSTEMM RREG M ISTERS COREBM O EM RYM AP
ADSP-BF561
Figure 3. Memory Map
The fourth on-chip memory system is the L2 SRAM memory array which provides 128K bytes of high speed SRAM operating at one half the bandwidth of the core, and slightly longer latency than the L1 memory banks. The L2 memory is a unified instruction and data memory and can hold any mixture of code and data required by the system design. The Blackfin cores share a dedicated low-latency 64-bit wide data path port into the L2 SRAM memory. Each Blackfin core processor has its own set of core Memory Mapped Registers (MMRs) but share the same system MMR registers and 128 KB L2 SRAM memory.
(SDRAM) as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices. The PC133-compliant SDRAM controller can be programmed to interface to up to four banks of SDRAM, with each bank containing between 16M bytes and 128M bytes providing access to up to 512M bytes of SDRAM. Each bank is independently programmable and is contiguous with adjacent banks regardless of the sizes of the different banks or their placement. This allows flexible configuration and upgradability of system memory while allowing the core to view all SDRAM as a single, contiguous, physical address space. The asynchronous memory controller can also be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a
External (Off-Chip) Memory
The ADSP-BF561 external memory is accessed via the External Bus Interface Unit (EBIU). This interface provides a glueless connection to up to four banks of synchronous DRAM
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ADSP-BF561
64M-byte segment regardless of the size of the devices used so that these banks will only be contiguous if fully populated with 64M bytes of memory.
Preliminary Technical Data
The ADSP-BF561 event controller consists of two stages, the Core Event Controller (CEC) and the System Interrupt Controller (SIC). The Core Event Controller works with the System Interrupt Controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G-byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The core MMRs are accessible only by the core and only in supervisor mode and appear as reserved space by on-chip peripherals. The system MMRs are accessible by the core in supervisor mode and can be mapped as either visible or reserved to other devices, depending on the system protection model desired.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15-7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG15-14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF561. Table 1 describes the inputs to the CEC, identifies their names in the Event Vector Table (EVT), and lists their priorities. Table 1. Core Event Controller (CEC)
Priority (0 is Highest) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Event Class Emulation/Test Reset Non-Maskable Exceptions Global Enable Hardware Error Core Timer General Interrupt 7 General Interrupt 8 General Interrupt 9 General Interrupt 10 General Interrupt 11 General Interrupt 12 General Interrupt 13 General Interrupt 14 General Interrupt 15 EVT Entry EMU RST NMI EVX IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Booting
The ADSP-BF561 contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF561 is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM.
Event Handling
The event controller on the ADSP-BF561 handles all asynchronous and synchronous events to the processor. The ADSPBF561 provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The controller provides support for five different types of events: * Emulation - An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. * Reset - This event resets the processor. * Non-Maskable Interrupt (NMI) - The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut down of the system. * Exceptions - Events that occur synchronously to program flow, i.e., the exception will be taken before the instruction is allowed to complete. Conditions such as data alignment violations, undefined instructions, etc. cause exceptions. * Interrupts - Events that occur asynchronously to program flow. They are caused by timers, peripherals, input pins, and an explicit software instruction. Each event has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack.
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources, to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF561 provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the Interrupt Assignment Registers (IAR). Table 2 describes the inputs into the SIC and the default mappings into the CEC.
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Preliminary Technical Data
Table 2. Peripheral Interrupt Source Reset State
Peripheral Interrupt Source PLL wakeup DMA1 Error DMA2 Error IMDMA Error PPI1 Error PPI2 Error SPORT0 Error SPORT1 Error SPI Error UART Error Reserved DMA1 0 interrupt DMA1 1 interrupt DMA1 2 interrupt DMA1 3 interrupt DMA1 4 interrupt DMA1 5 interrupt DMA1 6 interrupt DMA1 7 interrupt DMA1 8 interrupt DMA1 9 interrupt DMA1 10 interrupt DMA1 11 interrupt DMA2 0 interrupt DMA2 1 interrupt DMA2 2 interrupt DMA2 3 interrupt DMA2 4 interrupt DMA2 5 interrupt DMA2 6 interrupt DMA2 7 interrupt DMA2 8 interrupt DMA2 9 interrupt DMA2 10 interrupt DMA2 11 interrupt Timer0 interrupt Timer1 interrupt Timer2 interrupt Timer3 interrupt Timer4 interrupt Timer5 interrupt Timer6 interrupt Timer7 interrupt Timer8 interrupt Timer9 interrupt Timer10 interrupt Chan1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 IVG2 IVG07 IVG07 IVG07 IVG07 IVG07 IVG07 IVG07 IVG07 IVG07 IVG07 IVG07 IVG08 IVG08 IVG08 IVG08 IVG08 IVG08 IVG08 IVG08 IVG08 IVG08 IVG08 IVG08 IVG09 IVG09 IVG09 IVG09 IVG09 IVG09 IVG09 IVG09 IVG09 IVG09 IVG09 IVG09 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 Peripheral Interrupt Source Timer11 interrupt FIO0 interrupt A FIO0 interrupt B FIO1 interrupt A FIO1 interrupt B FIO2 interrupt A FIO2 interrupt B DMA1 write/read 0 interrupt DMA1 write/read1 interrupt DMA2 write/read 0 interrupt DMA2 write/read 1 interrupt IMDMA write/read 0 interrupt IMDMA write/read 1 interrupt Watchdog Timer Reserved Reserved Supplemental 0 Supplemental 1
1 2
ADSP-BF561
Table 2. Peripheral Interrupt Source Reset State (Continued)
Chan1 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 IVG2 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG08 IVG08 IVG09 IVG09 IVG12 IVG12 IVG13 IVG07 IVG07 IVG07 IVG07
Peripheral Interrupt Channel Number Default User IVG Interrupt
Event Control
The ADSP-BF561 provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each of the registers, as follows, is 16-bits wide, while each bit represents a particular event class: * CEC Interrupt Latch Register (ILAT) - The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but may be written only when its corresponding IMASK bit is cleared. * CEC Interrupt Mask Register (IMASK) - The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event thereby preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read from or written to while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) * CEC Interrupt Pending Register (IPEND) - The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode.
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The SIC allows further control of event processing by providing six 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 2. * SIC Interrupt Mask Register (SIC_IMASK0, SIC_IMASK1) - This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and will be processed by the system when asserted. A cleared bit in the register masks the peripheral event thereby preventing the processor from servicing the event. * SIC Interrupt Status Register (SIC_ISTAT0, SIC_ISTAT1) - As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, a cleared bit indicates the peripheral is not asserting the event. * SIC Interrupt Wakeup Enable Register (SIC_IWR0, SIC_IWR1)- By enabling the corresponding bit in this register, each peripheral can be configured to wake up the processor, should the processor be in a powered down mode when the event is generated. (For more information, see Dynamic Power Management on Page 11.) Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the mode of the processor.
Preliminary Technical Data
The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to +/- 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly. Examples of DMA types supported by the ADSP-BF561 DMA controllers include: * A single, linear buffer that stops upon completion * A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer * 1-D or 2-D DMA using a linked list of descriptors * 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, each DMA Controller has four memory DMA channels provided for transfers between the various memories of the ADSP-BF561 system. These enable transfers of blocks of data between any of the memories--including external SDRAM, ROM, SRAM, and flash memory--with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptorbased methodology or by a standard register-based autobuffer mechanism. Further, the ADSP-BF561 has a four channel Internal Memory DMA (IMDMA) Controller. The IMDMA Controller allows data transfers between any of the internal L1 and L2 memories.
WATCHDOG TIMERS
Each ADSP-BF561 core includes a 32-bit timer, which can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state, via generation of a hardware reset, nonmaskable interrupt (NMI), or general- purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register, which is set only upon a watchdog generated reset. The timer is clocked by the system clock (SCLK), at a maximum frequency of SCLK.
DMA CONTROLLERS
The ADSP-BF561 has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the DSP core. DMA transfers can occur between the ADSPBF561's internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The ADSP-BF561 DMA controllers support both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.
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Preliminary Technical Data
SERIAL PORTS (SPORTS)
The ADSP-BF561 incorporates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: * I2S capable operation. * Bidirectional operation - Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio. * Buffered (8-deep) transmit and receive ports - Each port has a data register for transferring data words to and from other DSP components and shift registers for shifting data in and out of the data registers. * Clocking - Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. * Word length - Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first. * Framing - Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync. * Companding in hardware - Each SPORT can perform A-law or -law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. * DMA operations with single-cycle overhead - Each SPORT can automatically receive and transmit multiple buffers of memory data. The DSP can link or chain sequences of DMA transfers between a SPORT and memory. * Interrupts - Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through DMA. * Multichannel capability - Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.
ADSP-BF561
provide a full duplex, synchronous serial interface, which supports both master and slave modes and multimaster environments. Each SPI port's baud rate and clock phase/polarities are programmable (see SPI Clock Rate equation), and each has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI's DMA controller can only service unidirectional accesses at any given time. f SCLK SPI Clock Rate = ---------------------------------2 x SPIBAUD During transfers, the SPI ports simultaneously transmit and receive by serially shifting data in and out on their two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
UART PORT
The ADSP-BF561 provides a full duplex Universal Asynchronous Receiver/Transmitter (UART) ports (UART0 and UART1) fully compatible with PC-standard UARTs. The UART ports provide a simplified UART interface to other peripherals or hosts, supporting full duplex, DMA supported, asynchronous transfers of serial data. Each UART port includes support for 5 to 8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The UART ports support two modes of operation, as follows: * PIO (Programmed I/O) - The processor sends or receives data by writing or reading I/O-mapped UATX or UARX registers, respectively. The data is double-buffered on both transmit and receive. * DMA (Direct Memory Access) - The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. Each UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower priority than most DMA channels because of their relatively low service rates. Each UART port's baud rate (see UART Clock Rate equation), serial data format, error code generation and status, and interrupts are programmable. In the UART Clock Rate equation, the divisor (D) can be 1 to 65536. f SCLK UART Clock Rate = --------------16 x D The UART programmable features include: * Supporting bit rates ranging from (fSCLK/ 1048576) to (fSCLK/16) bits per second. * Supporting data formats from 7 to12 bits per frame. * Both transmit and receive operations can be configured to generate maskable interrupts to the processor. In conjunction with the general-purpose timer functions, autobaud detection is supported.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF561 has one SPI-compatible ports that enable the processor to communicate with multiple SPI-compatible devices. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSIx, and Master InputSlave Output, MISO) and a clock pin (Serial Clock, SCK). One SPI chip select input pin (SPISS) let other SPI devices select the DSP, and seven SPI chip select output pins (SPISEL7-1) let the DSP select other SPI devices. The SPI select pins are reconfigured Programmable Flag pins. Using these pins, the SPI ports
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The capabilities of UART0 are further extended with support for the InfraRed Data Association (IrDA(R)) Serial InfraRed Physical Layer Link Specification (SIR) protocol.
Preliminary Technical Data
addition to the twelve general-purpose programmable timers, another timer is also provided for each core. These extra timers are clocked by the internal processor clock (CCLK) and is typically used as a system tick clock for generation of operating system periodic interrupts.
PROGRAMMABLE FLAGS (PFX)
The ADSP-BF561 has 48 bi-directional, general-purpose I/O, Programmable Flag (PF47-0) pins. The Programmable Flag pins have special functions for SPI port operation. Each programmable flag can be individually controlled as follows by manipulation of the flag control, status, and interrupt registers: * Flag Direction Control Register - Specifies the direction of each individual PFx pin as input or output. * Flag Control and Status Registers - Rather than forcing the software to use a read-modify-write process to control the setting of individual flags, the ADSP-BF561 employs a "write one to set" and "write one to clear" mechanism that allows any combination of individual flags to be set or cleared in a single instruction, without affecting the level of any other flags. Two control registers are provided, one register is written to in order to set flag values while another register is written to in order to clear flag values. Reading the flag status register allows software to interrogate the sense of the flags. * Flag Interrupt Mask Registers - The Flag Interrupt Mask Registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the Flag Control Registers that are used to set and clear individual flag values, one Flag Interrupt Mask Register sets bits to enable interrupt function, and the other Flag Interrupt Mask register clears bits to disable interrupt function. PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be configured to generate software interrupts. * Flag Interrupt Sensitivity Registers - The Flag Interrupt Sensitivity Registers specify whether individual PFx pins are level- or edge-sensitive and specify-if edge-sensitivewhether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE
The processor provides two Parallel Peripheral Interfaces (PPI) that can connect directly to parallel A/D and D/A converters, ITU-R-601/656 video encoders and decoders, and other general purpose peripherals. Each PPI consists of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. In ITU-R 656 mode, the PPI receives and parses a data stream of 8- bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported.
General Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle: * Data Receive with Internally Generated Frame Syncs. * Data Receive with Externally Generated Frame Syncs. * Data Transmit with Internally Generated Frame Syncs. * Data Transmit with Externally Generated Frame Syncs.
Input Mode
These modes support ADC/DAC connections, as well as video communication with hardware signaling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception / transmission of data.
ITU -R 656 Mode Descriptions
Three distinct ITU-R 656 modes are supported: * Active Video Only Mode * Vertical Blanking Only Mode * Entire Field Mode
TIMERS
There are fourteen (14) programmable timer units in the ADSPBF561. Twelve general-purpose timers have an external pin that can be configured either as a Pulse Width Modulator (PWM) or timer output, as an input to lock the timer, or for measuring pulse widths of external events. Each of the twelve general-purpose timer units can be independently programmed as a PWM, internally or externally clocked timer, or pulse width counter. The general-purpose timer units can be used in conjunction with the UART to measure the width of the pulses in the data stream to provide an auto-baud detect function for a serial channel. The general-purpose timers can generate interrupts to the processor core providing periodic events for synchronization, either to the processor clock or to a count of external signals. In
Active Video Only Mode
In this mode, the PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI.
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines.
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Preliminary Technical Data
Entire Field Mode
In this mode, the entire incoming bitstream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Though not explicitly supported, ITU,-656 output functionality can be achieved by setting up the entire frame structure (including active video, blanking and control information) in memory and streaming the data out of the PPI in a frame sync-less mode. The processor's 2D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on per-frame basis. These modes support ADC/DAC connections, as well as video communication with hardware signaling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data. Table 3. Power Settings (Continued)
Mode PLL
ADSP-BF561
PLL Core Bypassed Clock (CCLK) Sleep Enabled - Disabled Deep Sleep Disabled - Disabled Hibernate Disabled - Disabled System Clock (SCLK) Enabled Disabled Disabled Core Power On On Off
Hibernate Operating Mode--Maximum Static Power Savings
The Hibernate mode maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This disables both CCLK and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0 V to provide the lowest static power dissipation. Any critical information stored internally (memory contents, register contents, etc.) must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved. Since VDDEXT is still supplied in this mode, all of the external pins tri-state, unless otherwise specified. This allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. The internal supply regulator can be woken up by asserting the RESET pin.
DYNAMIC POWER MANAGEMENT
The ADSP-BF561 provides four operating modes, each with a different performance/power profile. In addition, Dynamic Power Management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the ADSPBF561 peripherals also reduces power consumption. See Table 3 for a summary of the power settings for each mode.
Full-On Operating Mode - Maximum Performance
In the Full-On mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the default execution state in which maximum performance can be achieved. The processor cores and all enabled peripherals run at full speed.
Sleep Operating Mode--High Dynamic Power Savings
The Sleep mode reduces power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event will wake up the processor. When in the Sleep mode, assertion of wakeup will cause the processor to sense the value of the BYPASS bit in the PLL Control register (PLL_CTL). When in the Sleep mode, system DMA access to L1 memory is not supported.
Active Operating Mode - Moderate Power Savings
In the Active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor's core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the Full-On mode is entered. DMA access is available to appropriately configured L1 memories. In the Active mode, it is possible to disable the PLL through the PLL Control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the Full-On or Sleep modes. Table 3. Power Settings
Mode PLL Core Bypassed Clock (CCLK) Enabled No Enabled Enabled/ Yes Enabled Disabled PLL System Core Clock Power (SCLK) Enabled On Enabled On
Deep Sleep Operating Mode--Maximum Dynamic Power Savings
The Deep Sleep mode maximizes power savings by disabling the clocks to the processor cores (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals will not be able to access internal resources or external memory. This powereddown mode can only be exited by assertion of the reset interrupt (RESET). If BYPASS is disabled, the processor will transition to the Full On mode. If BYPASS is enabled, the processor will transition to the Active mode.
Power Savings
As shown in Table 4, the ADSP-BF561 supports two different power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF561 into its own power domain, separate from the I/O,
Full On Active
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the processor can take advantage of Dynamic Power Management, without affecting the I/O devices. There are no sequencing requirements for the various power domains. Table 4. ADSP-BF561 Power Domains
Power Domain All internal logic I/O VDD Range VDDINT VDDEXT
Preliminary Technical Data
The Power Savings Factor is calculated as: Power Savings Factor f CCLKRED V DDINTRED 2 T RED = -------------------- x ------------------------- x ------------ T NOM f CCLKNOM V DDINTNOM
where the variables in the equations are: * fCCLKNOM is the nominal core clock frequency * fCCLKRED is the reduced core clock frequency * VDDINTNOM is the nominal internal supply voltage * VDDINTRED is the reduced internal supply voltage * TNOM is the duration running at fCCLKNOM * TRED is the duration running at fCCLKRED The percent power savings is calculated as: % Power Savings = ( 1 - Power Savings Factor ) x 100%
The power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic. The Dynamic Power Management feature of the ADSP-BF561 allows both the processor's input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled. The savings in power dissipation can be modeled using the Power Savings Factor and % Power Savings calculations.
VOLTAGE REGULATION
The ADSP-BF561 processor provides an on-chip voltage regulator that can generate processor core voltage levels 0.85V(-5% / +10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V supply. Figure 4 shows the typical external components required to complete the power management system. The regulator controls the internal logic voltage levels and is programmable with the Voltage Regulator Control Register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power (VDDEXT) supplied. While in hibernation, VDDEXT can still be applied, eliminating the need for external buffers. The voltage regulator can be activated from this powerdown state by asserting RESET, which will then initiate a boot sequence. The regulator can also be disabled and bypassed at the user's discretion.
Figure 4. Voltage Regulator Circuit
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Preliminary Technical Data
CLOCK SIGNALS
The ADSP-BF561 can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor's CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the ADSP-BF561 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 5 Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used.
ADSP-BF561
into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 5 illustrates typical system clock ratios: Table 5. Example System Clock Ratios
Signal Name SSEL[3-0] 0001 0110 1010 Divider Ratio Example Frequency Ratios VCO/SCLK (MHz) VCO SCLK 1:1 100 100 6:1 300 50 10:1 500 50
The maximum frequency of the system clock is fSCLK. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV). The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL[1-0] bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in Table 6. This programmable core clock capability is useful for fast core frequency modifications. Table 6. Core Clock Ratios
Signal Name CSEL[1-0] Divider Ratio Example Frequency Ratios VCO/CCLK VCO CCLK 1:1 500 500 2:1 500 250 4:1 200 50 8:1 200 25
CLKIN
XTAL
CLKOUT
Figure 5. External Crystal Connections
As shown in Figure 6, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user programmable 1x to 63x multiplication factor. The default multiplier is 10x, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register.
00 01 10 11
BOOTING MODES
The ADSP-BF561 has three mechanisms (listed in Table 7) for automatically loading internal L1 instruction memory after a reset. A fourth mode is provided to execute from external memory, bypassing the boot sequence. Table 7. Booting Modes
"FI NE" ADJUSTMENT REQUI RES PLL SEQUENCING
"COARSE" ADJUSTMENT ON-THE-FLY
x 1, 2, 4, 8 CLKIN PLL 1x - 63x
CCLK
BMODE1-0 00 01 10 11
VCO x 1:15 SCLK
SCLK CCLK SCLK 133 MHZ
Description Execute from 16-bit external memory (Bypass Boot ROM) Boot from 8/16-bit flash Reserved Boot from SPI serial ROM (16-bit address range)
Figure 6. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3-0 bits of the PLL_DIV register. The values programmed
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The BMODE pins of the Reset Configuration Register, sampled during power-on resets and software-initiated resets, implement the following modes: * Execute from 16-bit external memory - Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle R/W access times, 4-cycle setup). * Boot from 8/16-bit external FLASH memory - The 8/16-bit FLASH boot routine located in boot ROM memory space is set up using Asynchronous Memory Bank 0. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup). * Boot from SPI serial EEPROM (16-bit addressable) - The SPI uses the PF2 output pin to select a single SPI EPROM device, submits a read command at address 0x0000, and begins clocking data into the beginning of L1 instruction memory. A 16-bit addressable SPI-compatible EPROM must be used. For each of the boot modes, a boot loading protocol is used to transfer program and data blocks, from an external memory device, to their specified memory locations. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, Core A program execution commences from the start of L1 instruction SRAM (0xFFA0 0000). Core B remains in a heldoff state until a certain register bit is cleared. After that, Core B will start execution at address 0xFF60 0000. In addition, bit 4 of the Reset Configuration Register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory.
Preliminary Technical Data
* All registers, I/O, and memory are mapped into a unified 4G-byte memory space providing a simplified programming model. * Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and kernel stack pointers. * Code density enhancements, which include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded as 16-bits.
DEVELOPMENT TOOLS
The ADSP-BF561 is supported with a complete set of CROSSCORETM software and hardware development tools, including Analog Devices emulators and the VisualDSP++(R) development environment. The same emulator hardware that supports other Analog Devices processors also fully emulates the ADSP-BF561. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax, an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to Blackfin assembly. The Blackfin processor has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer's development schedule, increasing productivity. Statistical profiling enables the programmer to non intrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information) * Insert breakpoints * Set conditional breakpoints on registers, memory, and stacks * Trace instruction execution * Perform linear or statistical profiling of program execution
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set employs an algebraic syntax that was designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both a user (algorithm/application code) and a supervisor (O/S kernel, device drivers, debuggers, ISRs) mode of operations, allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the processor's unique architecture, offers the following advantages: * Seamlessly integrated DSP/CPU features are optimized for both 8-bit and 16-bit operations. * A multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle.
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Preliminary Technical Data
* Fill, dump, and graphically plot the contents of memory * Perform source level debugging * Create custom debugger windows The VisualDSP++ IDE lets programmers define and manage software development. Its dialog boxes and property pages let programmers configure and manage all development tools, including Color Syntax Highlighting in the VisualDSP++ editor. These capabilities permit programmers to: * Control how the development tools process inputs and generate outputs. * Maintain a one-to-one correspondence with the tool's command line switches. The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of embedded, real-time programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when Developing new application code. The VDK features include Threads, Critical and Unscheduled regions, Semaphores, Events, and Device flags. The VDK also supports Priority-based, Pre-emptive, Cooperative and TimeSliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used with standard command-line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system state, when debugging an application that uses the VDK. VCSE is Analog Devices technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. Download components from the Web and drop them into the application. Publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with the drag of the mouse, examine run time stack and heap usage. The Expert Linker is fully compatible with existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments. Analog Devices' emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF561 to monitor and control the target board processor during emulation. The emulator provides fullspeed emulation, allowing inspection and modification of memory, registers, and processor stacks. Non intrusive in-circuit
ADSP-BF561
emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processor family. Third Party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET)
The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on the ADSP-BF561. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the processor's JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices web site (www.analog.com)-- use site search on "EE-68." This document is updated regularly to keep pace with improvements to emulator support. To use these emulators, the target board must include a header that includes a header that connects the processor's JTAG port to the emulation.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-BF561 architecture and functionality. For detailed information on the Blackfin DSP family core architecture and instruction set, refer to the ADSP-BF561 Hardware Reference and the Blackfin Family Instruction Set Reference.
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PIN DESCRIPTIONS
ADSP-BF561 pin definitions are listed in Table 8. Unused inputs should be tied or pulled to VDDEXT or GND. Table 8. Pin Descriptions
Block EBIU Pin Name ADDR[25:2] DATA[31:0] ABE[3:0]/SDQM[3:0] BG BR EBIU (SDRAM) BGH SRAS SCAS SWE SCKE SCLK0/CLKOUT SCLK1 SA10 SMS[3:0] AMS[3:0] ARDY AOE AWE ARE PPI1D[15:8] /PF[47:40] PPI1D[7:0] PPI1CLK PPI1SYNC1/ TMR8 PPI1SYNC2/ TMR9 PPI1SYNC3 PPI2D[15:8] /PF[39:32] PPI2D[7:0] PPI2CLK PPI2SYNC1/ TMR10 PPI2SYNC2/ TMR11 PPI2SYNC3 EMU TCK TDO TDI TMS TRST Type Signals Function O I/O O O I O O O O O O O O O O I O O O I/O I/O I I/O I/O I/O I/O I/O I I/O I/O I/O O I O I I I 24 32 4 1 1 1 1 1 1 1 1 1 1 4 4 1 1 1 1 8 8 1 1 1 1 8 8 1 1 1 1 1 1 1 1 1 1 Address Bus for Async/Sync Access Data Bus for Async/Sync Access Byte Enables/Data Masks for Async /Sync Access Bus Grant Bus Request Bus Grant Hang Row Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output Pin 0 Clock Output Pin 1 SDRAM A10 Pin Bank Select Bank Select Hardware Ready Control Output Enable Write Enable Read Enable PPI Data / Programmable Flag Pins PPI Data Pins PPI Clock PPI Sync / Timer PPI Sync / Timer PPI Sync PPI Data / Programmable Flag Pins PPI Data Pins PPI Clock PPI Sync / Timer PPI Sync / Timer PPI Sync Emulation Output JTAG Clock JTAG Serial Data Out JTAG Serial Data In JTAG Mode Select JTAG Reset
Preliminary Technical Data
Driver Pull-up/down requirement Type none A A A A none none none pull-up required if function not used none none none none none none none none none none pull-up required if function not used none none none software configurable, none software configurable, none software configurable, none software configurable, none software configurable, none software configurable, none software configurable, none software configurable, none software configurable, none software configurable, none software configurable, none software configurable, none none internal pull-down none internal pull-down internal pull-down external down necessary if JTAG not used
A A A A A B B A A A A A A C C C C C C C C C C C C -
EBIU (ASYNC)
PPI1
PPI2
JTAG
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Preliminary Technical Data
Table 8. Pin Descriptions (Continued)
Block UART Pin Name RX/PF27 TX/PF26 SPI MOSI MISO SCK SPORT0 RSCLK0/PF28 RFS0/PF19 DR0PRI DR0SEC/PF20 TSCLK0/PF29 TFS0/PF16 DT0PRI/PF18 DT0SEC/PF17 SPORT1 RSCLK1/PF30 RFS1/PF24 DR1PRI DR1SEC/PF25 TSCLK1/PF31 TFS1/PF21 DT1PRI/PF23 DT1SEC/PF22 Type Signals Function I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 UART Receive / Programmable Flag UART Transmit / Programmable Flag Master Out Slave In Master In Slave Out SPI Clock Sport0 / Programmable Flag Sport0 Receive Frame Sync / Programmable Flag Sport0 Receive Data Primary Sport0 Receive Data Secondary / Programmable Flag Sport0 Transmit Serial Clock / Programmable Flag Sport0 Transmit Frame Sync / Programmable Flag Sport0 Transmit Data Primary / Programmable Flag Sport0 Transmit Data Secondary / Programmable Flag Sport1 / Programmable Flag Sport1 Receive Frame Sync / Programmable Flag Sport1 Receive Data Primary Sport1 Receive Data Secondary / Programmable Flag Sport1 Transmit Serial Clock / Programmable Flag Sport1 Transmit Frame Sync / Programmable Flag Sport1 Transmit Data Primary / Programmable Flag Sport1 Transmit Data Secondary / Programmable Flag
ADSP-BF561
Driver Pull-up/down requirement Type C software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary C pull-up is necessary if booting via SPI D software configurable, no pull-up/down necessary D software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary D software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary D software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary D software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary
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ADSP-BF561
Table 8. Pin Descriptions (Continued)
Block PF/TIMER Pin Name PF15/EXT CLK PF14 PF13 PF12 PF11 PF10 PF9 PF8 PF7/SPISEL7/ TMR7 PF6/SPISEL6/ TMR6 PF5/SPISEL5/ TMR5 PF4/SPISEL4/ TMR4 PF3/SPISEL3/ TMR3 PF2/SPISEL2/ TMR2 PF1/SPISEL1/ TMR1 PF0/SPISS/ TMR0 CLKIN XTAL RESET SLEEP BMODE[1:0] Type Signals Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I O I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
Preliminary Technical Data
Driver Pull-up/down requirement Type Programmable Flag C software configurable, / external timer clock input no pull-up/down necessary Programmable Flag C software configurable, no pull-up/down necessary Programmable Flag C software configurable, no pull-up/down necessary Programmable Flag C software configurable, no pull-up/down necessary Programmable Flag C software configurable, no pull-up/down necessary Programmable Flag C software configurable, no pull-up/down necessary Programmable Flag C software configurable, no pull-up/down necessary Programmable Flag C software configurable, no pull-up/down necessary Programmable Flag / SPI Select C software configurable, / Timer no pull-up/down necessary Programmable Flag / SPI Select C software configurable, / Timer no pull-up/down necessary Programmable Flag / SPI Select C software configurable, / Timer no pull-up/down necessary Programmable Flag / SPI Select C software configurable, / Timer no pull-up/down necessary Programmable Flag / SPI Select C software configurable, / Timer no pull-up/down necessary Programmable Flag / SPI Select C software configurable, / Timer no pull-up/down necessary Programmable Flag / SPI Select C software configurable, / Timer no pull-up/down necessary Programmable Flag / Slave SPI Select C software configurable, / Timer no pull-up/down necessary Clock input needs to be at a level or clocking Crystal connection none Chip reset signal always active if core power on Sleep C none Dedicated Mode Pin, Configures pull-up or pull-down required the boot mode that is employed following a hardware reset or software reset PLL BYPASS control pull-up or pull-down required Non Maskable interrupt Core A pull-down required if function not used Non Maskable interrupt Core B pull-down required if function not used Regulation output N/A
Clock Generator Mode Controls
BYPASS NMI0 NMI1 Regulator VROUT1-0
I I I O
1 1 1 2
Rev. PrC |
Page 18 of 52 |
April 2004
Preliminary Technical Data
Table 8. Pin Descriptions (Continued)
Block Supplies Pin Name VDDEXT VDDINT GND No Connection Type Signals Function P P G NC 23 14 41 2 256 Power Supply Power Supply Power Supply Return NC Driver Type -
ADSP-BF561
Pull-up/down requirement N/A N/A N/A N/A
Total pins
Rev. PrC |
Page 19 of 52 |
April 2004
ADSP-BF561
SPECIFICATIONS
Note that component specifications are subject to change without notice.
Preliminary Technical Data
RECOMMENDED OPERATING CONDITIONS
Parameter VDDINT VDDEXT VIH VIL TAMBIENT Parameter Internal Supply Voltage External Supply Voltage High Level Input Voltage1, @ VDDEXT =maximum Low Level Input Voltage2, @ VDDEXT =minimum Ambient Operating Temperature Industrial Commercial Minimum 0.8 2.25 2.0 -0.3 -40 0 Nominal 1.2 2.5 or 3.3 Maximum TBD 3.6 3.6 0.6 85 70 Unit V V V V C C
1
The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bi-directional and input only pins.
ELECTRICAL CHARACTERISTICS
Parameter VOH High Level Output Voltage1 VOL Low Level Output Voltage1 IIL Low Level Input Current2 High Level Input Current3 IIH IIH High Level Input Current4 IOZH Three-State Leakage Current5 IOZL Three-State Leakage Current5 CIN Input Capacitance6, 7
1 2
Test Conditions @ VDDEXT =3.0V, IOH = -0.5 mA @ VDDEXT =3.0V, IOL = 2.0 mA @ VDDEXT =maximum, VIN = 0 V @ VDDEXT =maximum, VIN = VDD maximum @ VDDEXT =maximum, VIN = VDD maximum @ VDDEXT = maximum, VIN = VDD maximum @ VDDEXT = maximum, VIN = 0 V fIN = 1 MHz, TAMBIENT = 25C, VIN = 2.5 V
Minimum 2.4 -10
Maximum 0.4 10 50 10
-10 TBD
Unit V V V A A A A pF
Applies to output and bidirectional pins. Applies to all input pins. 3 Applies to all input pins except TCK, TDI, TMS, and TRST. 4 Applies to TCK, TDI, TMS, and TRST. 5 Applies to three-statable pins. 6 Applies to all signal pins. 7 Guaranteed, but not tested.
Rev. PrC |
Page 20 of 52 |
April 2004
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage1 (VDDINT) External (I/O) Supply Voltage1 (VDDEXT) Input Voltage1 Output Voltage Swing1 Load Capacitance1 ,2 Core Clock (CCLK)1 ADSP-BF561SKBCZ600 ADSP-BF561SKBCZ500 System Clock (SCLK)1 Storage Temperature Range1 Junction Temperature Under Bias Lead Temperature (5 seconds)1
1
ADSP-BF561
-0.3 V to +1.4 V -0.3 V to +3.8 V -0.5 V to 3.6 V -0.5 V to VDDEXT +0.5 V 200 pF 600 MHz 500 MHz 133 MHz -65C to +150C 125C 185C
Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3V) or 30 pF (at 2.5V) for ADDR25-2, DATA31-0, ABE3-0/SDQM3-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.
ESD SENSITIVITY
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-BF561 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrC |
Page 21 of 52 |
April 2004
ADSP-BF561
TIMING SPECIFICATIONS
Table 9 and Table 12 describe the timing requirements for the ADSP-BF561 clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock, system clock and Voltage Controlled Oscillator (VCO) operating fre-
Preliminary Technical Data
quencies, as described in Absolute Maximum Ratings on Page 21. Table 12 describes Phase-Locked Loop operating conditions.
Table 9. Core and System Clock Requirements--ADSP-BF561SKBCZ500
Parameter tCCLK Core Cycle Period (VDDINT =1.4 V- 50 mV) Core Cycle Period (VDDINT =1.35 V-5%) tCCLK tCCLK Core Cycle Period (VDDINT =1.2 V-5%) tCCLK Core Cycle Period (VDDINT =1.1 V-5%) tCCLK Core Cycle Period (VDDINT =1.0 V-5%) tCCLK Core Cycle Period (VDDINT =0.9 V-5%) tCCLK Core Cycle Period (VDDINT =0.8 V) Minimum na na 2 2.25 2.70 3.20 4.00 Maximum Unit ns ns ns ns ns ns ns
Table 10. Core and System Clock Requirements--ADSP-BF561SKBCZ600X
Parameter tCCLK Core Cycle Period (VDDINT =1.4 V- 50 mV) Core Cycle Period (VDDINT =1.35 V-5%) tCCLK tCCLK Core Cycle Period (VDDINT =1.2 V-5%) tCCLK Core Cycle Period (VDDINT =1.1 V-5%) tCCLK Core Cycle Period (VDDINT =1.0 V-5%) tCCLK Core Cycle Period (VDDINT =0.9 V-5%) tCCLK Core Cycle Period (VDDINT =0.8 V) Minimum na na 1.66 2.25 2.70 3.20 4.00 Maximum Unit ns ns ns ns ns ns ns
Table 11. Core and System Clock Requirements--ADSP-BF561SBB600
Parameter tCCLK Core Cycle Period (VDDINT =1.4 V- 50 mV) tCCLK Core Cycle Period (VDDINT =1.35 V-5%) Core Cycle Period (VDDINT =1.2 V-5%) tCCLK tCCLK Core Cycle Period (VDDINT =1.1 V-5%) tCCLK Core Cycle Period (VDDINT =1.0 V-5%) tCCLK Core Cycle Period (VDDINT =0.9 V-5%) tCCLK Core Cycle Period (VDDINT =0.8 V) Minimum na 1.66 2.0 2.25 2.70 3.20 4.00 Maximum Unit ns ns ns ns ns ns ns
Table 12. Phase-Locked Loop Operating Conditions
Parameter Voltage Controlled Oscillator (VCO) Frequency Minimum 50 Maximum Maximum CCLK Unit MHz
Rev. PrC |
Page 22 of 52 |
April 2004
Preliminary Technical Data
Clock and Reset Timing
Table 13 and Figure 7 describe clock and reset operations. Per Figure 7, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 600/133 MHz. Table 13. Clock and Reset Timing
Parameter Timing Requirements CLKIN Period tCKIN tCKINL CLKIN Low Pulse1 tCKINH CLKIN High Pulse1 tWRST RESET Asserted Pulsewidth Low2 Switching Characteristics tSCLK CLKOUT Period3
1 2
ADSP-BF561
Min 25.0 10.0 10.0 11 tCKIN 7.54
Max 100.0
Unit ns ns ns ns ns
Applies to bypass mode and non-bypass mode. Applies after power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted, assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator). 3 The figure below shows a x2 ratio between tCKIN and tSCLK, but the ratio has many programmable options. For more information, see the System Design chapter of the ADSPBF561 Hardware Reference. 4 tSCLK must always also be larger than tCCLK.
tCKIN
CLKIN
tCKINL
RESET
tCKINH tWRST
tSCLKD
CLKOUT
tSCLK
Figure 7. Clock and Reset Timing
Rev. PrC |
Page 23 of 52 |
April 2004
ADSP-BF561
Asynchronous Memory Read Cycle Timing
Table 14. Asynchronous Memory Read Cycle Timing
Parameter Timing Requirements tSDAT tHDAT tSARDY tHARDY DATA15-0 Setup Before CLKOUT DATA15-0 Hold After CLKOUT ARDY Setup Before CLKOUT ARDY Hold After CLKOUT
Preliminary Technical Data
Min
Max
Unit
2.1 0.8 4.0 0.0
ns ns ns ns
Switching Characteristic tDO tHO
1
Output Delay After CLKOUT1 Output Hold After CLKOUT 1 0.8
6.0
ns ns
Output pins include AMS3-0, ABE3-0, ADDR25-2, AOE, ARE.
SETUP 2 CYCLES
PROGRAMMED READ ACCESS 4 CYCLES
ACCESS EXTENDED 3 CYCLES
HOLD 1 CYCLE
CLKOUT
t DO
AMSx
t HO
ABE1-0 ADDR19-1
BE, ADDRESS
AOE
t DO
ARE
tHO
t SARDY
ARDY
tHARDY
t HARDY
t SARDY
t SDAT t HDAT
DATA15-0
READ
Figure 8. Asynchronous Memory Read Cycle Timing
Rev. PrC |
Page 24 of 52 |
April 2004
Preliminary Technical Data
Asynchronous Memory Write Cycle Timing
Table 15. Asynchronous Memory Write Cycle Timing
Parameter Timing Requirements tSARDY tHARDY ARDY Setup Before CLKOUT ARDY Hold After CLKOUT 4.0 0.0 Min Max
ADSP-BF561
Unit
ns ns
Switching Characteristic tDDAT tENDAT tDO tHO
1
DATA15-0 Disable After CLKOUT DATA15-0 Enable After CLKOUT Output Delay After CLKOUT1 Output Hold After CLKOUT 1 0.8 1.0
6.0
ns ns
6.0
ns ns
Output pins include AMS3-0, ABE3-0, ADDR25-2, DATA31-0, AOE, AWE.
SETUP 2 CYCLES
PROGRAMMED WRITE ACCESS 2 CYCLES
ACCESS EXTENDED 1 CYCLE
HOLD 1 CYCLE
CLKOUT
t DO
AMSx
t HO
ABE1-0 ADDR19-1
BE, ADDRESS
tDO
AWE
tHO
t SARDY
ARDY
t HARDY
t END AT
DATA15-0 WRITE DATA
tSARDY
t DD AT
Figure 9. Asynchronous Memory Write Cycle Timing
Rev. PrC |
Page 25 of 52 |
April 2004
ADSP-BF561
SDRAM Interface Timing
Table 16. SDRAM Interface Timing
Parameter Timing Requirement tSSDAT tHSDAT DATA Setup Before CLKOUT DATA Hold After CLKOUT
Preliminary Technical Data
Min
Max
Unit
2.1 0.8
ns ns
Switching Characteristic tSCLK tSCLKH tSCLKL tDCAD tHCAD tDSDAT tENSDAT
1
CLKOUT Period CLKOUT Width High CLKOUT Width Low Command, ADDR, Data Delay After CLKOUT1 Command, ADDR, Data Hold After CLKOUT1 Data Disable After CLKOUT Data Enable After CLKOUT
7.5 2.5 2.5 6.0 0.8 6.0 1.0
ns ns ns ns ns ns ns
Command pins include: SRAS, SCAS, SWE, SDQM, SMS3-0, SA10, SCKE.
tSCLK
CLKOUT
tSCLKH
t SSDAT tHSDAT
DATA (IN)
t SCLKL
t DCAD tENSDAT
DATA(OUT)
tD SDA T tHCAD
tDCAD
CMND ADDR (OUT)
tHCAD
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 10. SDRAM Interface Timing
Rev. PrC |
Page 26 of 52 |
April 2004
Preliminary Technical Data
External Port Bus Request and Grant Cycle Timing
Table 17 and Figure 11 describe external port bus request and bus grant operations. Table 17. External Port Bus Request and Grant Cycle Timing
Parameter, 1, 2 Timing Requirements tBS tBH BR asserted to CLKOUT high setup CLKOUT high to BR de-asserted hold time 4.6 0.0 Min Max
ADSP-BF561
Unit
ns ns
Switching Characteristics tSD tSE tDBG tEBG tDBH tEBH
1 2
CLKOUT low to SMS, address, and RD/WR disable CLKOUT low to SMS, address, and RD/WR enable CLKOUT high to BG asserted setup CLKOUT high to BG de-asserted hold time CLKOUT high to BGH asserted setup CLKOUT high to BGH de-asserted hold time
4.5 4.5 3.6 3.6 3.6 3.6
ns ns ns ns ns ns
These are preliminary timing parameters that are based on worst-case operating conditions. The pad loads for these timing parameters are 20 pF.
CLKOUT
tB S
BR
tB H
tS D tS E
AMSx
tS D
tS E
A D D R 2 5 -2 A B E 3 -0
tS D tS E
AWE ARE
tD B G
BG
tE B G
tD B H
BGH
tE B H
Figure 11. External Port Bus Request and Grant Cycle Timing
Rev. PrC |
Page 27 of 52 |
April 2004
ADSP-BF561
Parallel Peripheral Interface Timing
Table 18, Figure 12, describes Parallel Peripheral Interface operations. Table 18. Parallel Peripheral Interface Timing
Parameter Timing Requirements tPCLKW PPIx_CLK Width1 tPCLK PPI_CLK Period1 Timing Requirements tSFSPE External Frame Sync Setup Before PPI_CLK External Frame Sync H old After PPI_CLK tHFSPE tSDRPE Receive Data Setup Before PPI_CLK tHDRPE Receive Data Hold After PPI_CLK Switching Characteristics tDFSPE Internal Frame Sync Delay After PPI_CLK tHOFSPE Internal Frame Sync Hold After PPI_CLK Transmit Data Delay After PPI_CLK tDDTPE tHDTPE Transmit Data Hold After PPI_CLK
1
Preliminary Technical Data
Min 6.0 15.0 3.0 3.0 TBD TBD
Max
Unit ns ns ns ns ns ns
10.0 0.0 10.0 0.0
ns ns ns ns
PPI_CLK frequency cannot exceed fSCLK/2
D R IV E EDGE
SAM PLE EDGE
tP C LK W
P P I_ C L K
tD F S P E tH O F S P E
P P I_ F S 1 P P I_ F S 2
tS F S P E
tH F SP E
tD D T P E tH D T P E
P P Ix
tSD R PE
tH D R P E
Figure 12. Timing Diagram PPI
Rev. PrC |
Page 28 of 52 |
April 2004
Preliminary Technical Data
Serial Ports
Table 19 through Table 24 on Page 30 and Figure 13 on Page 31 through Figure 15 on Page 33 describe Serial Port operations. Table 19. Serial Ports--External Clock
Parameter Timing Requirements tSFSE tHFSE tSDRE tHDRE tSCLKW tSCLK
1
ADSP-BF561
Min
Max
Unit
TFS/RFS Setup Before TSCLK/RSCLK1 TFS/RFS Hold After TSCLK/RSCLK1 Receive Data Setup Before RSCLK1 Receive Data Hold After RSCLK1 TSCLK/RSCLK Width TSCLK/RSCLK Period
3.0 3.0 3.0 3.0 4.5 15.0
ns ns ns ns ns ns
Referenced to sample edge.
Table 20. Serial Ports--Internal Clock
Parameter Timing Requirements tSFSI tHFSI tSDRI tHDRI tSCLKW tSCLK
1
Min
Max
Unit
TFS/RFS Setup Before TSCLK/RSCLK1 TFS/RFS Hold After TSCLK/RSCLK1 Receive Data Setup Before RSCLK1 Receive Data Hold After RSCLK TSCLK/RSCLK Width TSCLK/RSCLK Period
1
TBD TBD 6.0 0.0 4.5 15.0
ns ns ns ns ns ns
Referenced to sample edge.
Table 21. Serial Ports--External Clock
Parameter Switching Characteristics tDFSE tHOFSE tDDTE tHDTE
1
Min
Max
Unit
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1 TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1 Transmit Data Delay After TSCLK Transmit Data Hold After TSCLK1
1
10.0 0.0 10.0 0.0
ns ns ns ns
Referenced to drive edge.
Rev. PrC |
Page 29 of 52 |
April 2004
ADSP-BF561
Table 22. Serial Ports--Internal Clock
Parameter Switching Characteristics tDFSI tHOFSI tDDTI tHDTI tSCLKIW
1
Preliminary Technical Data
Min Max Unit
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1 TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1 Transmit Data Delay After TSCLK1 Transmit Data Hold After TSCLK1 TSCLK/RSCLK Width TBD 4.5 TBD
TBD
ns ns
TBD
ns ns ns
Referenced to drive edge.
Table 23. Serial Ports--Enable and Three-State
Parameter Switching Characteristics tDTENE tDDTTE tDTENI tDDTTI
1
Min
Max
Unit
Data Enable Delay from External TSCLK1 Data Disable Delay from External TSCLK1 Data Enable Delay from Internal TSCLK Data Disable Delay from Internal TSCLK1
TBD TBD TBD TBD
ns ns ns ns
Referenced to drive edge.
Table 24. External Late Frame Sync
Parameter Switching Characteristics tDDTLFSE tDTENLFSE
1 2
Min
Max
Unit
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01,2 Data Enable from late FS or MCE = 1, MFD = 01,2 TBD
TBD
ns ns
MCE = 1, TFS enable and TFS valid follow tDDTENFS and tDDTLFSE. If external RFS/TFS setup to RSCLK/TSCLK > tSCLK/2 then tDDTLSCK and tDTENLSCK apply, otherwise tDDTLFSE and tDTENLFS apply.
Rev. PrC |
Page 30 of 52 |
April 2004
Preliminary Technical Data
DATA RECEIVE-- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE-- EXTERNAL CLOCK DRIVE EDGE
ADSP-BF561
SAMPLE EDGE
tSCLKIW
RCLK RCLK
tSCLKW
t DFSE t HOFSE
RFS
t DFSE t SFSI t HFSI
RFS
tHO FSE
t SFSE
tHFSE
t SDRI
DR
tHD RI
DR
t SDRE
t HDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT -- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT -- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
TCLK TCLK
t SCLKW
t DFSI t HOFSI
TFS
tDFSE t SFSI t HFSI
TFS
tHO FSE
t SFSE
t HFSE
t HDTI
DT
t DDTI
DT
t HDTE
t DDTE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE TCLK (EXT) TFS ("LATE", EXT) TCLK/RCLK
DRIVE EDGE
t DDTEN
DT
t DDTTE
DRIVE EDGE TCLK (INT) TFS ("LATE", INT) TCLK/RCLK
DRIVE EDGE
t DDTIN
t DDTTI
DT
Figure 13. Serial Ports
Rev. PrC |
Page 31 of 52 |
April 2004
ADSP-BF561
EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE RSCLK SAMPLE DRIVE
Preliminary Technical Data
tSFSE/I
tHOFSE/I
RFS
tDDTENFS
tDDTE/I tHDTE/I
1ST BIT 2ND BIT
DT
tDDTLFSE
LATE EXTERNAL TFS DRIVE TSCLK SAMPLE DRIVE
tSFSE/I
tHOFSE/I
TFS
tDDTENFS
DT
tDDTE/I tHDTE/I
1ST BIT 2ND BIT
tDDTLFSE
Figure 14. External Late Frame Sync (Frame Sync Setup < tSCLK/2)
Rev. PrC |
Page 32 of 52 |
April 2004
Preliminary Technical Data
EXTERNAL RFS WITH MCE=1, MFD=0 DRIVE SAMPLE DRIVE
ADSP-BF561
RSCLK
tSFSE/I
tHOFSE/I
RFS
tDDTE/I tDTENLSCK tHDTE/I
DT
1ST BIT
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS DRIVE SAMPLE DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I tDTENLSCK tHDTE/I
2ND BIT
DT
1ST BIT
tDDTLSCK
Figure 15. External Late Frame Sync (Frame Sync Setup > tSCLK/2)
Rev. PrC |
Page 33 of 52 |
April 2004
ADSP-BF561
Serial Peripheral Interface (SPI) Port--Master Timing
Table 25 and Figure 16 describe SPI port master operations. Table 25. Serial Peripheral Interface (SPI) Port--Master Timing
Parameter Timing Requirements tSSPIDM tHSPIDM Data input valid to SCK edge (data input setup) SCK sampling edge to data input invalid
Preliminary Technical Data
Min
Max
Unit
TBD TBD
ns ns
Switching Characteristics tSDSCIM tSPICHM tSPICLM tSPICLK tHDSM tSPITDM tDDSPIDM tHDSPIDM SPISELx low to first SCK edge Serial clock high period Serial clock low period Serial clock period Last SCK edge to SPISELx high Sequential transfer delay SCK edge to data out valid (data out delay) SCK edge to data out invalid (data out hold) 2tSCLK-1.5 2tSCLK-1.5 2tSCLK-1.5 4tSCLK-1.5 2tSCLK-1.5 2tSCLK-1.5 TBD TBD TBD TBD ns ns ns ns ns ns ns ns
Rev. PrC |
Page 34 of 52 |
April 2004
Preliminary Technical Data
SPISELx (OUTPUT)
ADSP-BF561
tSDSCIM
SCK (CPOL = 0) (OUTPUT)
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tSPICLM
SCK (CPOL = 1) (OUTPUT)
tSPICHM
tDDSPIDM
MOSI (OUTPUT) CPHA=1 MISO (INPUT) MSB
tHDSPIDM
LSB
tSSPIDM
MSB VALID
tHSPIDM
tSSPIDM
LSB VALID
tHSPIDM
tDDSPIDM
MOSI (OUTPUT) CPHA=0 MISO (INPUT) MSB
tHDSPIDM
LSB
tSSPIDM
MSB VALID
tHSPIDM
LSB VALID
Figure 16. Serial Peripheral Interface (SPI) Port--Master Timing
Rev. PrC |
Page 35 of 52 |
April 2004
ADSP-BF561
Serial Peripheral Interface (SPI) Port--Slave Timing
Table 26 and Figure 17 describe SPI port slave operations. Table 26. Serial Peripheral Interface (SPI) Port--Slave Timing
Parameter Timing Requirements tSPICHS tSPICLS tSPICLK tHDS tSPITDS tSDSCI tSSPID tHSPID Serial clock high period Serial clock low period Serial clock period Last SCK edge to SPISS not asserted Sequential Transfer Delay SPISS assertion to first SCK edge Data input valid to SCK edge (data input setup) SCK sampling edge to data input invalid
Preliminary Technical Data
Min
Max
Unit
2tSCLK-1.5 2tSCLK-1.5 4tSCLK-1.5 2tSCLK-1.5 2tSCLK-1.5 2tSCLK-1.5 1.6 1.6
ns ns ns ns ns ns ns ns
Switching Characteristics tDSOE tDSDHI tDDSPID tHDSPID SPISS assertion to data out active SPISS deassertion to data high impedance SCK edge to data out valid (data out delay) SCK edge to data out invalid (data out hold) 0 0 0 0 8 8 10 10 ns ns ns ns
Rev. PrC |
Page 36 of 52 |
April 2004
Preliminary Technical Data
ADSP-BF561
SPISS (INPUT)
tSPICHS
SCK (CPOL = 0) (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
SCK (CPOL = 1) (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPID tHDSPID tDDSPID tDSDHI
LSB
MISO (OUTPUT) CPHA=1 MOSI (INPUT)
MSB
tSSPID
MSB VALID
tHSPID
tSSPID
tHSPID
LSB VALID
tDSOE
MISO (OUTPUT) CPHA=0 MOSI (INPUT)
tDDSPID
MSB LSB
tDSDHI
tHSPID tSSPID
MSB VALID LSB VALID
Figure 17. Serial Peripheral Interface (SPI) Port--Slave Timing
Rev. PrC |
Page 37 of 52 |
April 2004
ADSP-BF561
Universal Asynchronous Receiver-Transmitter (UART) Port--Receive and Transmit Timing
Figure 18 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in Figure 18 there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.
Preliminary Technical Data
CLKOUT (SAMPLE CLOCK)
RXD
DATA(5-8) STOP
RECEIVE INTERNAL UART RECEIVE INTERRUPT
UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ
START TXD AS DATA WRITEN TO BUFFER UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT DATA(5-8) STOP (1-2)
TRANSMIT INTERNAL UART TRANSMIT INTERRUPT
Figure 18. UART Port--Receive and Transmit Timing
Rev. PrC |
Page 38 of 52 |
April 2004
Preliminary Technical Data
Timer Cycle Timing
Table 27 and Figure 19 describe timer expired operations. The input signal is asynchronous in "width capture mode" and "external clock mode" and has an absolute maximum input frequency of fSCLK/2 MHz. Table 27. Timer Cycle Timing
Parameter Timing Characteristics tWL tWH Timer Pulsewidth Input Low1 Timer Pulsewidth Input High1 1 1 Min Max
ADSP-BF561
Unit
SCLK cycles SCLK cycles
Switching Characteristic tHTO
1 2
Timer Pulsewidth Output2
1
(232-1)
SCLK cycles
The minimum pulsewidths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPICLK input pins in PWM output mode. The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232-1) cycles.
CLKOUT
tHTO
TMRx (PWM OUTPUT MODE)
TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES)
tWL
tWH
Figure 19. Timer PWM_OUT Cycle Timing
Rev. PrC |
Page 39 of 52 |
April 2004
ADSP-BF561
Programmable Flags Cycle Timing
Table 28 and Figure 20 describe programmable flag operations. Table 28. Programmable Flags Cycle Timing
Parameter Timing Requirement tWFI Flag input pulsewidth
Preliminary Technical Data
Min
Max
Unit
tSCLK + 1
ns
Switching Characteristic tDFO Flag output delay from CLKOUT low TBD ns
CLKOUT
tDFO
PF (OUTPUT) FLAG OUTPUT
tWFI
PF (INPUT) FLAG INPUT
Figure 20. Programmable Flags Cycle Timing
Rev. PrC |
Page 40 of 52 |
April 2004
Preliminary Technical Data
JTAG Test And Emulation Port Timing
Table 29 and Figure 21 describe JTAG port operations. Table 29. JTAG Port Timing
Parameter Timing Parameters tTCK tSTAP tHTAP tSSYS tHSYS tTRSTW TCK Period TDI, TMS Setup Before TCK High TDI, TMS Hold After TCK High System Inputs Setup Before TCK High1 System Inputs Hold After TCK High1 TRST Pulsewidth
2
ADSP-BF561
Min
Max
Unit
20 4 4 4 5 4
ns ns ns ns ns TCK cycles
Switching Characteristics tDTDO tDSYS
1
TDO Delay from TCK Low System Outputs Delay After TCK Low3 0
10 12
ns ns
System Inputs=DATA31-0, ARDY, TMR2-0, PF47-0, PPIx_CLK, RSCLK0-1, RFS0-1, DR0PRI, DR0SEC, TSCLK0-1, TFS0-1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX, RESET, NMI, BMODE1-0, BR, PPIxD7-0. 2 50 MHz max. 3 System Outputs=DATA31-0, ADDR25-2, ABE3-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS3-0, PF47-0, RSCLK0-1, RFS0-1, TSCLK01, TFS0-1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPIxD7-0.
tTCK
TCK
tSTAP
TMS TDI
tHTAP
tDTDO
TDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure 21. JTAG Port Timing
Rev. PrC |
Page 41 of 52 |
April 2004
ADSP-BF561
POWER DISSIPATION
Total power dissipation has two components, one due to internal circuitry (PINT) and one due to the switching of external output drivers (PEXT). Table 30 shows the power dissipation for internal circuitry (VDDINT). Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Table 30. Internal Power Dissipation
Test Conditions1 Parameter fCCLK = fCCLK = 50 MHz 400 MHz VDDINT = VDDINT = 0.8 V 1.2 V TBD TBD IDDTYP2 IDDSLEEP3 TBD TBD TBD IDDDEEPSLEEP TBD
3
Preliminary Technical Data
The external component is calculated using: P EXT = O x C x V
2 DD
xf
The frequency f includes driving the load high and then back low. For example: DATA15-0 pins can drive high and low at a maximum rate of 1/(23tSCLK) while in SDRAM burst mode. A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation. P Total = P EXT + ( I DD x V DDINT )
fCCLK = 600 MHz VDDINT = 1.2 V 520 TBD 70 TBD
fCCLK = 600 MHz VDDINT = 1.35 V TBD TBD TBD TBD
Unit
mA mA mA A
IDDHI1 2
TBD
4
TBD
Note that the conditions causing a worst-case PEXT differ from those causing a worst-case PINT . Maximum PINT cannot occur while 100% of the output pins are switching from all ones (1s) to all zeros (0s). Note also that it is not common for an application to have 100%,or even 50%, of the outputs switching simultaneously.
BERNATE
IDD data is specified for typical process parameters. All data at 25C. Processor executing 75% dual Mac, 25% ADD with moderate data bus activity. 3 See the ADSP-BF53x Blackfin Processor Hardware Reference Manual for definitions of Sleep and Deep Sleep operating modes. 4 Measured at VDDEXT = 3.65V with voltage regulator off (VDDINT = 0V).
OUTPUT DRIVE CURRENTS
Figure 22 shows typical I-V characteristics for the output drivers of the ADSP-BF561. The curves represent the current drive capability of the output drivers as a function of output voltage.
120
SOURCE (VDDEXT) CURRENT - mA
The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on * The number of output pins that switch during each cycle (O) * The maximum frequency at which they can switch (f) * Their load capacitance (C) * Their voltage swing (VDDEXT)
100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 2 2.5 SOURCE (VDDEXT) VOLTAGE - V 3 3.5
TB
D
Figure 22. ADSP-BF561 Typical Drive
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in Timing Specifications on Page 22. These include output disable time, output enable time, and capacitive loading. The timing specifications for the DSP apply for the voltage reference levels
in Figure 23.
INPUT OR OUTPUT
1.5V
1.5V
Figure 23. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
Rev. PrC |
Page 42 of 52 |
April 2004
Preliminary Technical Data
Output Enable Time
Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the Output Enable/Disable diagram (Figure 24). The time tENA_MEASURED is the interval from when the reference signal switches to when the output voltage reaches 2.0V (output high) or 1.0V (output low). Time tTRIP is the interval from when the output starts driving to when the output reaches the 1.0V or 2.0V trip voltage. Time tENA is calculated as tENA_MEASURED-tTRIP. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
ADSP-BF561
time. A typical V will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (i.e., tDSDAT for an SDRAM write cycle).
5
OUTPUT DELAY OR HOLD - ns
4
3
2
TB
D
Output Disable Time
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by V is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the following equation: t DECAY = ( C L V ) I L The output disable time tDIS is the difference between tDIS_MEASURED and tDECAY as shown in Figure 24.The time tDIS_MEASURED is the interval from when the reference signal switches to when the output voltage decays V from the measured output high or output low voltage. tDECAY is calculated with test loads CL and IL, and with V equal to 0.5 V.
1
NOMINAL
-5 0 30 60 90 120 150 LOAD CAPACITANCE - pF 180 210
Figure 25. Typical Output Delay or Hold vs. Load Capacitance (at Max Case Temperature)
REFERENCE SIGNAL
tDIS-MEASURED tDIS
VOH (MEASURED) VOL (MEASURED)
tENA-MEASURED tENA
VOH (MEASURED) - V VOL (MEASURED) + V
VOH 2.0V (MEASURED) 1.0V VOL (MEASURED)
tDECAY
tTRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V.
Figure 24. Output Enable/Disable
EXAMPLE SYSTEM HOLD TIME CALCULATION
To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the ADSP-BF561's output voltage and the input threshold for the device requiring the hold
Rev. PrC |
Page 43 of 52 |
April 2004
ADSP-BF561
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 26 on Page 44). Figure 25 shows graphically how output delays and holds vary with load capacitance (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on Page 43). The graphs of Figure 25, Figure 27 and Figure 28 may not be linear outside the ranges shown, for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (10%-90%, V=Min) vs. Load Capacitance.
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
50V TO OUTPUT PIN 1.5V
Preliminary Technical Data
RISE AND FALL TIMES - ns (0.v - v, 20% - 80%)
TB
D
0
20
40
60 80 100 120 140 LOAD CAPACITANCE - pF
160
180
200
Figure 28. Typical Output Rise/Fall Time (10%-90%, Vddext = Min)
20pF
Figure 26. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0
RISE AND FALL TIMES - ns (.v - v, 20% - 80%)
D TB
0
20
40
60 80 100 120 140 LOAD CAPACITANCE - pF
160
180
200
Figure 27. Typical Output Rise/Fall Time (10%-90%, Vddext = Max)
Rev. PrC |
Page 44 of 52 |
April 2004
Preliminary Technical Data
256-BALL MBGA PIN CONFIGURATIONS
Table 31. 256-Lead MBGA Pin Assignments
MBGA Pin No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 Pin Name VDDEXT ADDR24 ADDR20 VDDEXT ADDR14 ADDR10 AMS3 AWE VDDEXT SMS3 SCLK0/CLKOUT SCLK1 BG ABE2/SDQM2 ABE3/SDQM3 VDDEXT GND PPI1D11/PF43 PPI1D12/PF44 PPI1SYNC1/TMR8 ADDR15 ADDR13 AMS2 VDDINT SMS0 SWE ABE0/SDQM0 DATA2 GND DATA4 DATA7 VDDEXT MBGA Pin No. B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 Pin Name PPI2CLK ADDR22 ADDR18 ADDR16 ADDR12 VDDEXT AMS1 ARE SMS1 SCKE VDDEXT BR ABE1/SDQM1 ADDR06 ADDR04 DATA0 CLKIN VDDEXT RESET PPI1D10/PF42 ADDR21 ADDR17 VDDINT GND VDDINT GND ADDR08 DATA10 DATA8 DATA12 DATA9 DATA11 MBGA Pin No. C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 Pin Name PPI1SYNC2/TMR9 PPI1CLK ADDR25 ADDR19 GND ADDR11 AOE AMS0 SMS2 SRAS GND BGH GND ADDR07 DATA1 DATA3 XTAL GND VDDEXT BYPASS PPI1D14/PF46 GND GND GND VDDINT ADDR05 ADDR03 DATA15 DATA14 GND DATA13 VDDEXT MBGA Pin No. D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16
ADSP-BF561
Pin Name PPI1D13/PF45 PPI1D15/PF47 PPI1SYNC3 ADDR23 GND GND ADDR09 GND ARDY SCAS SA10 VDDEXT ADDR02 GND DATA5 DATA6 GND GND PPI1D9/PF41 PPI1D7 PPI1D5 VDDINT VDDINT GND GND GND VDDINT DATA16 DATA18 DATA20 DATA17 DATA19
Rev. PrC |
Page 45 of 52 |
April 2004
ADSP-BF561
Table 31. 256-Lead MBGA Pin Assignments (Continued)
MBGA Pin No. J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 Pin Name VROUT0 VROUT1 PPI1D2 PPI1D3 PPI1D1 VDDEXT GND VDDINT VDDINT VDDINT GND DATA30 DATA22 GND DATA21 DATA23 PPI2D12/PF36 PPI2D10/PF34 PPI2D3 PPI2D1 PF1/SPISEL1/TMR1 PF9 GND PF13 TDO BMODE1 MOSI GND RFS1/PF24 GND DT0SEC/PF17 TSCLK0/PF29 MBGA Pin No. K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 Pin Name PPI1D6 PPI1D4 PPI1D8/PF40 PPI2SYNC1/TMR10 PPI2D14/PF38 VDDEXT GND VDDINT GND GND VDDINT DATA28 DATA26 DATA24 DATA25 VDDEXT PPI2D8/PF32 GND PPI2D5 PF0/SPISS/TMR0 GND PF5/SPISEL5/TMR5 PF11 PF15/EXTCLK GND TRST NMI0 GND RSCLK1/PF30 TFS1/PF21 RSCLK0/PF28 DR0SEC/PF20 MBGA Pin No. L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 Pin Name PPI1D0
Preliminary Technical Data
MBGA Pin No. M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 Pin Name PPI2D15/PF39 PPI2D13/PF37 PPI2D9/PF33 GND NC PF3/SPISEL3/TMR3 PF7/SPISEL7/TMR7 VDDINT GND BMODE0 SCK DR1PRI NC VDDEXT DATA31 DT0PRI/PF18 VDDEXT PPI2D4 VDDEXT PF2/SPISEL2/TMR2 PF6/SPISEL6/TMR6 VDDEXT PF12 VDDEXT TCK TMS SLEEP VDDEXT RX/PF27 DR1SEC/PF25 DT1SEC/PF22 VDDEXT
PPI2SYNC2/TMR11 GND PPI2SYNC3 VDDEXT PPI2D11/PF35 GND VDDINT GND VDDEXT GND DR0PRI TFS0/PF16 GND DATA27 DATA29 PPI2D7 PPI2D6 PPI2D2 PPI2D0 PF4/SPISEL4/TMR4 PF8 PF10 PF14 NMI1 TDI BR MISO TX/PF26 TSCLK1/PF31 DT1PRI/PF23 RFS0/PF19
Rev. PrC |
Page 46 of 52 |
April 2004
Preliminary Technical Data
297-BALL PBGA PIN CONFIGURATIONS
Table 32. 297-Lead PBGA Pin Assignments
MBGA Pin No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA01 AA02 AA25 AA26 AB01 AB02 Pin Name GND ADDR25 ADDR23 ADDR21 ADDR19 ADDR17 ADDR15 ADDR13 ADDR11 ADDR09 AMS3 AMS1 AWE ARE SMS0 SMS2 SRAS SCAS SCLK0/CLKOUT SCLK1 BGH ABE0/SDQM0 ABE2/SDQM2 ADDR08 ADDR06 GND PPI2D13/PF37 PPI2D12/PF36 DT0SEC/PF17 TSCLK0/PF29 PPI2D11/PF35 PPI2D10/PF34 MBGA Pin No. AB03 AB24 AB25 AB26 AC01 AC02 AC03 AC04 AC23 AC24 AC25 AC26 AD01 AD02 AD03 AD04 AD05 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 Pin Name GND GND TFS0/PF16 DR0PRI PPI2D9/PF33 PPI2D8/PF32 GND GND GND GND DR0SEC/PF20 RFS0/PF19 PPI2D7 PPI2D6 GND GND GND GND GND GND NC RSCLK0/PF28 PPI2D5 GND PPI2D3 PPI2D1 PF0/SPISS/TMR0 PF2/SPISEL2/TMR2 PF4/SPISEL4/TMR4 PF6/SPISEL6/TMR6 PF8 PF10 MBGA Pin No. AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 Pin Name PF12 PF14 NC TDO TRST EMU BMODE1 BMODE0 MISO MOSI RX/PF27 RFS1/PF24 DR1SEC/PF25 TFS1/PF21 GND NC GND PPI2D4 PPI2D2 PPI2D0 PF1/SPISEL1/TMR1 PF3/SPISEL3/TMR3 PF5/SPISEL5/TMR5 PF7/SPISEL7/TMR7 PF9 PF11 PF13 PF15/EXT CLK NMI1 TCK TDI TMS MBGA Pin No. AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22
ADSP-BF561
Pin Name SLEEP NMI0 SCK TX/PF26 RSCLK1/PF30 DR1PRI TSCLK1/PF31 DT1SEC/PF22 DT1PRI/PF23 GND PPI2CLK GND ADDR24 ADDR22 ADDR20 ADDR18 ADDR16 ADDR14 ADDR12 ADDR10 AMS2 AMS0 AOE ARDY SMS1 SMS3 SCKE SWE SA10 BR BG ABE1/SDQM1
Rev. PrC |
Page 47 of 52 |
April 2004
ADSP-BF561
Table 32. 297-Lead PBGA Pin Assignments (Continued)
MBGA Pin No. B23 B24 B25 B26 C01 C02 C03 C04 C05 C22 C23 C24 C25 C26 D01 D02 D03 D04 D23 D24 D25 D26 E01 E02 E03 E24 E25 E26 F01 F02 F25 F26 Pin Name ABE3/SDQM3 ADDR07 GND ADDR05 PPI1SYNC3 PPI1CLK GND GND GND GND GND GND ADDR04 ADDR03 PPI1SYNC1/TMR8 PPI1SYNC2/TMR9 GND GND GND GND ADDR02 DATA1 PPI1D15/PF47 PPI1D14/PF46 GND GND DATA0 DATA3 PPI1D13/PF45 PPI1D12/PF44 DATA2 DATA5 MBGA Pin No. G01 G02 G25 G26 H01 H02 H25 H26 J01 J02 J10 J11 J12 J13 J14 J15 J16 J17 J18 J25 J26 K01 K02 K10 K11 K12 K13 K14 K15 K16 K17 K18 Pin Name PPI1D11/PF43 PPI1D10/PF42 DATA4 DATA7 BYPASS RESET DATA6 DATA9 CLKIN GND VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT DATA8 DATA11 XTAL NC VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT MBGA Pin No. K25 K26 L01 L02 L10 L11 L12 L13 L14 L15 L16 L17 L18 L25 L26 M01 M02 M10 M11 M12 M13 M14 M15 M16 M17 M18 M25 M26 N01 N02 N10 N11 Pin Name DATA10 DATA13 NC NC VDDEXT GND GND GND GND GND GND GND VDDINT DATA12 DATA15 VROUT0 GND VDDEXT GND GND GND GND GND GND GND VDDINT DATA14 DATA17 VROUT1
Preliminary Technical Data
MBGA Pin No. N12 N13 N14 N15 N16 N17 N18 N25 N26 P01 P02 P10 P11 P12 P13 P14 P15 P16 P17 P18 P25 P26 R01 R02 R10 R11 R12 R13 R14 R15 R16 R17 Pin Name GND GND GND GND GND GND VDDINT DATA16 DATA19 PPI1D7 PPI1D8/PF40 VDDEXT GND GND GND GND GND GND GND VDDINT DATA18 DATA21 PPI1D5 PPI1D6 VDDEXT GND GND GND GND GND GND GND
PPI1D9/PF41 VDDEXT GND
Rev. PrC |
Page 48 of 52 |
April 2004
Preliminary Technical Data
Table 32. 297-Lead PBGA Pin Assignments (Continued)
MBGA Pin No. R18 R25 R26 T01 T02 T10 T11 T12 T13 T14 T15 Pin Name VDDINT DATA20 DATA23 PPI1D3 PPI1D4 VDDEXT GND GND GND GND GND MBGA Pin No. T16 T17 T18 T25 T26 U01 U02 U10 U11 U12 U13 Pin Name GND GND VDDINT DATA22 DATA25 PPI1D1 PPI1D2 VDDEXT VDDEXT VDDEXT VDDEXT MBGA Pin No. U14 U15 U16 U17 U18 U25 U26 V01 V02 V25 V26 Pin Name GND VDDINT VDDINT VDDINT VDDINT DATA24 DATA27 PPI2SYNC3 PPI1D0 DATA26 DATA29 MBGA Pin No. W01 W02 W25 W26 Y01 Y02 Y25 Y26
ADSP-BF561
Pin Name PPI2SYNC1/TMR10 PPI2SYNC2/TMR11 DATA28 DATA31 PPI2D15/PF39 PPI2D14/PF38 DATA30 DT0PRI/PF18
Rev. PrC |
Page 49 of 52 |
April 2004
ADSP-BF561
OUTLINE DIMENSIONS
Dimensions in the outline dimension figure are shown in millimeters.
Preliminary Technical Data
a
12.00 BSC SQ
256-BALL MINI BGA (BC-256)
9.75 BSC SQ 0.65 BSC BALL PITCH CL
A1 BALL PAD CORNER
A1 BALL PAD CORNER
A B C D E F G H J K L M N P R T
CL
TOP VIEW
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
BOTTOM VIEW
1.70 1.51 1.36 SIDE VIEW
0.25 MIN DETAIL A
NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-225, WITH NO EXACT PACKAGE SIZE AND EXCEPTION TO PACKAGE HEIGHT. 3. MINIMUM BALL HEIGHT 0.25
0.10 MAX COPLANARITY SEATING PLANE DETAIL A
0.45 BALL DIAMETER 0.40 0.35
Figure 29. 256-Ball Mini-Ball Grid Array
Rev. PrC |
Page 50 of 52 |
April 2004
Preliminary Technical Data
OUTLINE DIMENSIONS
Dimensions in the outline dimension figure are shown in millimeters.
ADSP-BF561
a
27.00 BSC SQ
297-BALL PBGA (B-297)
25.00 BSC SQ 1.00 BSC BALL PITCH 8.00 CL
A1 BALL PAD CORNER
A1 BALL PAD CORNER
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
8.00 CL
TOP VIEW
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
2.43 2.23 2.03 SIDE VIEW
0.40 MIN DETAIL A
NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MS-034, VARIATION AAL-1. 3. MINIMUM BALL HEIGHT 0.40
0.20 MAX COPLANARITY SEATING PLANE DETAIL A
0.70 BALL DIAMETER 0.60 0.50
Figure 30. 297-Ball PBGA Grid Array
ORDERING GUIDE
Part Number ADSP-BF561SKBCZ600 ADSP-BF561SKBCZ500 ADSP-BF561SBB500 Ambient Temperature Range 0C to +70C 0C to +70C -40C to +85C Instruction Rate 600 MHz 500 MHz 500 MHz Operating Voltage 0.8 V to 1.2 V internal, 2.5 V or 3.3 V I/O 0.8 V to 1.2 V internal, 2.5 V or 3.3 V I/O 0.8 V to 1.2 V internal, 2.5 V or 3.3 V I/O
Rev. PrC |
Page 51 of 52 |
April 2004
ADSP-BF561
Preliminary Technical Data
Rev. PrC |
Page 52 of 52 |
April 2004

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